1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to complex integrated circuits that comprise metal gate electrode structures formed according to a replacement gate approach.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with a high performance in terms of speed and/or power consumption. A reduction of the size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors and resistors, are typically formed in integrated circuits as required by the basic circuit layout. Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be improved, but also their packing density may be significantly increased, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SOC).
With the increasing shrinkage of the features sizes of semiconductor-based circuit elements, such as transistors, thereby significantly increasing the overall complexity of the devices and the manufacturing processes, the complex wiring system also has to be adapted to the increasing number of circuit elements and the significantly increased packing density. Consequently, typically, in complex integrated circuits, a plurality of stacking wiring layers or metallization layers are required, in which metal lines and vias commonly establish the electrical connections as required by the circuit layout of the device under consideration. Due to the overall reduced feature sizes, the dimensions of metal lines and vias have also been continuously reduced, thereby requiring new strategies and materials for the complex metallization systems, since the high current densities and the close proximity of adjacent metal regions may result in non-acceptable thermal conditions and parasitic time constants when using well-established materials, such as silicon dioxide and aluminum. For this reason, copper in combination with so-called low-k dielectric materials are typically used in complex metallization systems which, however, may be associated with significant problems in view of the handling of copper in a semiconductor facility. It is well known that copper readily diffuses in a plurality of materials, such as silicon dioxide, silicon dioxide-based low-k dielectric materials and the like. However, copper diffusing into sensitive device areas, such as complex transistor elements, may significantly alter the transistor characteristics and may thus finally result in yield loss and reduced reliability of complex semiconductor devices. Therefore, copper material in metallization lines and vias has to be reliably confined, for instance on the basis of conductive and/or dielectric diffusion barrier materials, such as tantalum, tantalum nitride, silicon nitride and the like. Moreover, during the handling of copper material in a semiconductor production facility, any undue contamination of carrier materials and process tools and related equipment has to be suppressed as much as possible in view of transistor instabilities and the like. Furthermore, due to the complex metallization systems, a plurality of different material systems and reactive process atmospheres may have to be implemented in the overall process flow, which may also result in the diffusion of non-desired atomic species into sensitive device areas, thereby also contributing to variations of the device characteristics.
Consequently, in sophisticated semiconductor devices, an efficient diffusion barrier material, such as a silicon nitride material, may be provided above the transistor elements in order to prevent undue diffusion of copper and other unwanted species into the complex transistor elements. For this purpose, the contact level of the semiconductor device, i.e., the interlayer dielectric material provided in the device level so as to enclose and passivate the transistor elements, prior to forming any metallization layers, may include an appropriate silicon nitride material in combination with a silicon dioxide material, thereby obtaining a reliable confinement of a transistor element. In some recent developments in providing superior transistor elements, sophisticated gate electrode structures are provided in which a high-k dielectric material in combination with a metal-containing electrode material may be provided in a very advanced manufacturing stage, thereby, however, compromising integrity of the transistor elements, as will be explained in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a semiconductor device 100 in cross-sectional view which comprises a substrate 101 above which is formed a semiconductor layer 102. Typically, the substrate 101 may represent a silicon substrate, a silicon-on-insulator (SOI) substrate and the like. Similarly, the semiconductor layer 102 is a silicon-based material for forming therein and thereabove complex circuit elements, such as transistors 150A, 150B. The transistors 150A, 150B may comprise drain and source regions 151 in combination with metal silicide regions 152. Furthermore, the transistors 150A, 150B comprise gate electrode structures 160A, 160B, respectively, which may have a similar configuration for high performance transistors, even if the transistors 150A, 150B may represent transistors of different conductivity type. For example, the gate electrode structures 160A, 160B may comprise a gate dielectric material 163 in combination with a metal-containing cap material 162. Additionally, a polysilicon material 161 is provided, which may also be considered as a placeholder material since the material 161 will be replaced by a conductive material in a later manufacturing stage. Furthermore, the device 100 comprises a sidewall spacer structure 153 having any appropriate configuration so as to assist in forming the complex dopant profiles for the drain and source regions 151 and for providing the metal silicide regions 152. Additionally, a portion of a contact level 120 is provided in the form of dielectric materials 121 and 122, for instance in the form of silicon nitride and silicon dioxide, respectively.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following conventional process strategies. After forming appropriate isolation structures in the semiconductor layer 102, such as shallow trench isolations (not shown), the gate electrode structures 160A, 160B may be formed by providing material layers for the materials 163, 162 and 161, which may be accomplished on the basis of any appropriate deposition techniques, surface treatment processes and the like. It should be appreciated that the gate dielectric material 163 may comprise a high-k dielectric material which is to be understood as a dielectric material having a dielectric constant of 10.0 and higher. In sophisticated field effect transistors, the current flow in a channel region 154 between the drain and source regions 151 is controlled by the gate electrode structure, wherein, typically, a reduction in length of the channel region 154, i.e., in FIG. 1a, the horizontal extension of the channel region 154 between the drain and source regions 151, may be associated with an increase of performance of the transistors 150A, 150B. Since the channel length is substantially determined by the length of the gate electrode structures 160A, 160B, i.e., in FIG. 1a, the horizontal extension of the material 161, critical dimensions of 50 nm and less have to be implemented in highly sophisticated field effect transistors. The reduction of the channel length and thus of the gate length, however, comes along with a reduced controllability of the channel region 154 for given supply voltages, which may typically require an increased capacitive coupling of the gate electrode to the channel region 154, which in turn may be realized by reducing the thickness of a gate dielectric material. Upon further device scaling, a well-established dielectric material silicon dioxide, which has been used as a base material for gate dielectric materials, may no longer be appropriate since, typically, a thickness of 1 nm and less would be required for maintaining the controllability of the channel region 154, which in turn results in extremely increased leakage current through extremely thin silicon dioxide-based gate dielectric material. Therefore, in sophisticated applications, alternative materials are increasingly used, possibly in combination with an extremely thin silicon dioxide layer, in order to provide a physically greater thickness while nevertheless obtaining the desired high capacitive coupling. For example, hafnium oxide and the like may be used in sophisticated gate dielectric materials. On the other hand, the new gate dielectric materials may require a corresponding adaptation of the work function, which may require the provision of specific metal species to be provided at or in the gate dielectric material 163. To this end, sophisticated approaches have been proposed in which the work function of P-channel transistors and N-channel transistors may be adjusted in an early manufacturing stage, i.e., prior to or upon patterning the gate electrode structures 160A, 160B. Corresponding approaches, however, may be associated with a plurality of difficulties in view of maintaining the work function stability throughout the entire process flow, in particular throughout high temperature processes, as are typically required for forming the drain and source regions 151. For this reason, so-called replacement gate approaches have been developed in which the gate dielectric material 163 including the high-k material may be confined by the conductive cap material 162 followed by the standard polysilicon material 161, thereby enabling the patterning of the gate electrode structures 160A, 160B on the basis of well-established process techniques. On the other hand, an appropriate electrode material in combination with work function adjusting metal species may be provided in a late manufacturing stage, i.e., at the manufacturing stage as shown in FIG. 1a. Consequently, after patterning the gate electrode structures 160A, 160B, the drain and source regions 151 in combination with the spacer structure 153 may be formed, including any anneal processes, and afterwards the metal silicide regions 152 may be formed. Thereafter, the dielectric materials 121 and 122 may be deposited on the basis of well-established process techniques. For example, the material 121 may be provided as a silicon nitride material, for instance with a high internal stress level, so as to enhance performance of one or both of the transistors 150A, 150B. Thereafter, the silicon dioxide material 122 may be deposited, and subsequently a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to expose the placeholder material 161 of the gate electrode structures 160A, 160B. However, during the corresponding polishing process, the material 121 is also removed from above the gate electrode structures, thereby compromising the diffusion blocking effect of the contact level 120, which is typically provided by the material 121 having a high diffusion blocking effect, for instance with respect to copper.
FIG. 1b schematically illustrates the device 100 in a further advanced manufacturing stage. As illustrated, the gate electrode structure 160A comprises an electrode material 164, such as aluminum, in combination with an additional metal-containing layer 165A that is appropriate for obtaining the desired work function in the gate electrode structure 160A. Similarly, the gate electrode structure 160B comprises the electrode material 164 and a material layer 165B that is appropriate for obtaining the desired work function for the transistor 150B. The corresponding process sequence for replacing the material 161 (FIG. 1a) and providing the various material systems 165A, 165B in combination with the electrode material 164 may be performed on the basis of any appropriate process strategy. During the removal of any excess metal, typically, a further polishing process may be applied, thereby possibly further compromising the protective characteristics of the material layer 121.
FIG. 1c schematically illustrates the device 100 with a further dielectric material 123 of the contact level 120. The material 123, which may also be referred to as interlayer dielectric material, is typically comprised of silicon dioxide, which represents a well-established interlayer dielectric material. Consequently, the material 123 may be in direct contact with the gate electrode structures 160A, 160B and any underlying material layers, which have been exposed upon removing a portion of the dielectric material 121. Consequently, during the further processing of the device 100, a significantly reduced degree of diffusion blocking effects may be provided by the contact level 120, since silicon dioxide may be significantly less efficient compared to silicon nitride, for instance with respect to copper diffusion.
FIG. 1d schematically illustrates the device 100 in a further advanced manufacturing stage. As illustrated, contact elements 124 are provided in the contact level 120 and thus extend through the material 123 and possibly through the materials 122 and 121 in order to connect to various regions of the transistors 150A, 150B. The contact elements 124 comprise any appropriate conductive material, such as tungsten and aluminum, in sophisticated applications, copper may also be provided, and the like. Moreover, a metallization system 130, which for convenience is illustrated as a single metallization layer, is provided above the contact level 120 and may comprise any appropriate dielectric material 131 in combination with metal lines 132, which in turn may be comprised of copper in combination with conductive barrier materials, such as tantalum, tantalum nitride and the like. As previously discussed, upon forming the contact elements 124 and also during the process sequence for forming the metallization system 130, a plurality of critical materials and processes may have to be performed in which undue diffusion of specific species, in particular copper species, may occur through the various dielectric materials, thereby finally reaching the transistors 150A, 150B due to the reduced diffusion blocking effect of the silicon nitride layer 121. Hence, a pronounced variation of transistors characteristics may be caused, in particular if extremely scaled devices are considered. Thus, although a replacement gate approach may provide advantages in terms of stability of threshold voltages of the transistors due to a very late adjustment of the work function, the reduced integrity of the contact level may result in significant yield losses.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.